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2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com scg2500a i synchronous clock generator us headquarters: 630-851-4722 european headquarters: +353-61-472221 general description the scg2500ai is a mixed-signal phase lock loop generating cmos outputs from an intrinsically low jitter voltage controlled crystal oscillator. the scg2500ai is based on connor-winfield?s scg2500 series product line. the scg2500ai can lock to one of two possible reference inputs at 8 khz that are selectable using one input select pin. the scg2500ai has an improved filter compared to the scg2500. the new filter allows the scg2500ai to more closely track the selected input reference and lowers switching mties. the scg2500ai provides 3 alarm outputs, loss of reference a, (lor a) loss of reference b, (lor b), and loss of lock, (lol) as compared to the scg2500?s combined alarms. lol alarm is active when the phase error exceeds 1us. switching references within 100 ns will then comply with gr-253-core requirements. lor a and lor b independently monitor the input references. if both references are lost the unit will go into free run automatically. when both references are lost, the unit should be forced into free run (pin 5 = 1). lor a and lor b can then be monitored until the references return. refer to table 6 for more operational details. the reference output at 8 khz is derived from the oscillator output. phase alignment of the 8 khz output to the input cannot be guaranteed with dual input units. the package maximum dimensions are .780? x .830? x .350? on a six layer fr4 board with surface mount pins. parts are assembled using high temperature solder to withstand surface mount reflow processes. tri-state is not available with this model. features ? industrial temperature range (-40- 85c) phase locked output frequency control intrinsically low jitter crystal oscillator two selectable references @ 8 khz hitless reference switching 2 independent reference monitors lol alarm output force free run function automatic free run operation upon loss of both references input duty cycle tolerant 3.3 volt power supply small size: 0.78? x 0.83? x 0.35? maximum surface mount, dil package quick overview ref_in osc_out ref_out 8 khz 19.44 mhz 8 khz 8 khz 51.84 mhz 8 khz
preliminary data sheet #: sg071 p age 2 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice operating specifications table 2 parameter specifications notes voltage 3.3v 5% 1.0 current 150 ma @ 3.46v input frequency ref 1 and ref 2 8 khz 2.0 available oscillator output frequencies 19.44 mhz, 51.84 mhz reference output 8 khz 6.0 temperature range -40 to 85c input jitter tolerance 1us typical (jitter frequencies > 10 hz) jitter bandwidth < 10 hz acquisition time... ...from a 10ppm frequency step. apprx. 1 sec. for frequency lock ...from a reference switch. < 1 sec. for phase lock ...during start-up or from free run. 30 - 60 sec. for phase lock time to lol alarm off tbd capture/pull-in range 32 ppm minimum output duty cycle 45/55 % min/max @ 50% level output rise and fall time 3 ns @ 20% to 80% output level output load 30 pf alarm lor a, lor b, lol free run accuracy 20 ppm package fr4 sm 0.78? x 0.83? x 0.350? (maximum) mtie @ synchronization rearrangement gr-253-core, 1999 r5-136 4.0, 4.1 dynamic offset 40 ns 9.0 absolute maximum rating table 1 symbol parameter minimum nominal maximum units notes v cc power supply voltage -0.5 - +4.0 volts v i input voltage -0.5 - +5.5 volts t s storage temperature -65.0 - +150.0 c input and output characteristics table 3 symbol parameter minimum nominal maximum units notes v ih high level input voltage 2.0 - 5.5 v v il low level input voltage 0 - 0.8 v t io i/o to output valid - - 10 ns c out output capacitance - - 10 pf v ho high level output voltage loh = -4ma 2.40 - - - vcc min v io low level output voltage lo1 = 8ma - - 0.4 - vcc max t ir input reference signal pulse width 30 - - ns
preliminary data sheet #: sg071 p age 3 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: 1.0 requires external regulation 2.0 externally selectable via input select ab 3.0 from a 20 ppm offset in reference frequency 4.0 entry into free run doesn?t meet requirement for initial 2.33 seconds of self-timing 4.1 if the selected reference is removed, system response to the lol alarm must be less than 100ns 5.0 upon power-up, allow 60 seconds for the scg to obtain tight phase lock. 6.0 static offset will accumulate with each reference switch for the reference output only. 7.0 frequency will drift to lower limit rail if not switched. 8.0 loss of both references will automatically force free run. change the force free run (pin 5) to 1 upon detection of this condi tion. 9.0 phase drift from -40 to 85c. output jitter specifications table 4 jitter bw 10 hz - 20 mhz sonet jitter bw 12 khz - 20 mhz frequency (mhz) ps (rms) m ui ps (rms) m ui 19.44 10 typ. 0.194 typ. 1 max., 0.5 typ. 0.019 max. 51.84 10 typ. 0.518 typ. 1 max., 0.5 typ. 0.052 max. operational table table 5 inputs outputs select a/b ref a ref b force free run oscillator output ref out lol lor a lor b x a a 1 fr fr 0 1 1 xnaa 1 fr fr0 0 1 xana1 fr fr0 10 x na na 0 ** fr fr 0 0 0 0 a a 0 ra ra 1 1 1 0ana0 ra ra110 0naa 0 u u 0 0 1 1 a a 0 rb rb 1 1 1 1na a 0 rb rb 1 0 1 1ana0 u u0 10 notes: a = active na = not active fr = free run ra = locked to reference a rb = locked to reference b u = unstable (see note 7) x = don't care ** see note 8.0
preliminary data sheet #: sg071 p age 4 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice circuit board footprint figure 1 pin connection 1 filtered 8 khz output 2 tck (do not connect, factory use only) 3 tms (do not connect, factory use only) 4 ground 5 force free run / tdi (1 = free run) 6 lor a (1=active reference, 0=lor) 7 ref b 8 ref a 9 oscillator output 10 lor b (1=active reference, 0=lor) 11 vcc 12 tdo (do not connect, factory use only) 13 lol of active reference (1=locked, 0=unlocked) 14 input reference select ab (a = 0, b = 1) pin connections table 6 0.650 0.100 typ 0.050 typ 0.800 0.640 0.080 (16.51mm) (1.27mm) (16.26mm) (20.32mm) (2.03mm) 0.050 typ (1.27mm) (2.54mm) state machine refb refa select ab analog filter oscillator output 1 / n low jitter vcxo force free run lor b lor a lol of active reference 8 khz output dpfd 27 ? 33 ? 33 ? 2.2k ? 27 ? 10k ? 10k ? block diagram figure 2
preliminary data sheet #: sg071 p age 5 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice package maximum dimensions figure 3
preliminary data sheet #: sg071 p age 6 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice lol phase detector (internal signal) external reference (input a or b) internal reference (internal signal) lor (selected reference) 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 start-up region 1 1 1 us start-up region 1 8 khz reference input < 1 sec > 1 sec 1 sec 2 3 4 124 sec(min) to 374 sec(max) after lol minimum pulse width = 2 s during start-up, the lol alarm will pulse during the few seconds of operation 5 lor alarm diagram figure 4 alarmtiming legend use for all alarm timing diagrams table 7
preliminary data sheet #: sg071 p age 7 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice lol alarm diagram figure 5 lol phase detector (internal signal) external reference (selected input a or b) internal reference (internal signal) lor (selected reference) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 1 5 1 0
preliminary data sheet #: sg071 p age 8 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice meets eia-481a and eiaj-1009b 1.00 dia 250 pcs/reel maximum .08 3.15 13.00 8.45 dia .08 1.31 .08 direction of feed (customer) (33.27mm) (2.0mm) (2.0mm) (330.2mm) (80mm) (2.0mm) (214.6mm) dia (25.4mm) (bo) pocket size (ao) (ko) 20.92mm (.824") 21.17mm (.833") 9.49mm (.374") 32mm (1.26") width 32mm (1.26") pitch 6.99mm (.275") (ki) .374 3 ad (9.49mm) .014 (.36mm) (28.4mm) 1.118 .559 (14.2mm) .079 (2mm) dia. min. .059 (1.5mm) dia. .063 (1.6mm) dia. .069 (1.75mm) (4mm) .157 (2mm) .079 .063 (1.6mm) .059 (1.5mm) .065 .072 (1.85mm) (1.65mm) (ko) (20.92mm) .824 .833 (bo) (21.17mm) bd 3 1.26 (32.0mm) .275 (6.99mm) 1.260 (32.0mm) .236 (6.0mm) (1.93mm) .076 45 19.4 .383 (9.74mm) (6.00mm) .236 (3.00mm) .118 .138 (3.51mm) w p tape and reel packaging figure 6
preliminary data sheet #: sg071 p age 9 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice temp 0 100 150 200 250 50 12345678 time (minutes) (deg c) recommended reflow profile peak temp: 217 deg c max rise slope: 1.5 deg c/sec time above 150 c: 100 sec solder profile figure 7 ordering information scg{xxxx}-{fff.fff}{m} xxxx equals a specific model (2500a i ) fff.fff equals the oscillator output frequency ( 019.44, 051.84, or 077.76 ) m equals mhz and is added to all part numbers example: to order an scg2500a i with an oscillator output of 19.44 mhz, order part number scg2500a i -019.44m please contact connor-winfield for other frequencies that may be available.
preliminary data sheet #: sg071 p age 10 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice
preliminary data sheet #: sg071 p age 11 of 12 rev: p00 date: 03/07/03 ? copyright 2003 the connor-winfield corp. all rights reserved specifications subject to change without notice
revision revision date note p00 3/7/03 preliminary informational release

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